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Definition: PLD
(Programmable Logic Device) A variety of logic chips that are programmable at the customer's site, the customer being the actual user or a vendor that is reselling a customized chip. Logic programmability means that new chip designs can be tested and easily changed without incurring the huge photomask costs for chips completed in a semiconductor fab (see ASIC). In addition, memory-based PLDs can be reprogrammed over and over, which allows working products to be upgraded at the user's site.
FPGAs
Field programmable gate arrays are a major programmable logic technology that some vendors classify under the PLD umbrella while others keep them separate. In either case, both FPGAs and PLDs fall within the "field programmable device" (FPD) category (see FPGA).
Programmable Once (Fusible Links and Antifuse)
Fuse-based PLDs are permanent "one-time programmable" (OTP) chips. "Fusible links" are programmed by electrically melting conductive aluminum traces (blowing microscopic fuses). "Antifuse" is the opposite. Instead of destroying conducting links, they are "grown" by sending charges into tiny blocks of insulating silicon that become conductive.
Reprogrammable (Memory Based)
Reprogrammable PLDs store their logic design in an EPROM, EEPROM, flash or SRAM memory that associates each programmable connection point with a memory cell (is the connection open or closed). SRAM-based PLDs are popular and reloaded at startup, making them dynamic and adaptive to new requirements on the spur of the moment.
SPLDs and CPLDs
Simple PLDs (SPLDs) are devices with an AND array feeding an OR array or something similar, the differences being whether one or both arrays are programmable. SPLDs are programmed via fusible link, antifuse, EPROM, EEPROM or flash. Complex PLDs (CPLDs) are formed from a number of SPLDs connected together by a programmable switching matrix. CPLDs are EEPROM, flash or SRAM based.
The ASIC Family
FPGAs
Field programmable gate arrays are a major programmable logic technology that some vendors classify under the PLD umbrella while others keep them separate. In either case, both FPGAs and PLDs fall within the "field programmable device" (FPD) category (see FPGA).
Programmable Once (Fusible Links and Antifuse)
Fuse-based PLDs are permanent "one-time programmable" (OTP) chips. "Fusible links" are programmed by electrically melting conductive aluminum traces (blowing microscopic fuses). "Antifuse" is the opposite. Instead of destroying conducting links, they are "grown" by sending charges into tiny blocks of insulating silicon that become conductive.
Reprogrammable (Memory Based)
Reprogrammable PLDs store their logic design in an EPROM, EEPROM, flash or SRAM memory that associates each programmable connection point with a memory cell (is the connection open or closed). SRAM-based PLDs are popular and reloaded at startup, making them dynamic and adaptive to new requirements on the spur of the moment.
SPLDs and CPLDs
Simple PLDs (SPLDs) are devices with an AND array feeding an OR array or something similar, the differences being whether one or both arrays are programmable. SPLDs are programmed via fusible link, antifuse, EPROM, EEPROM or flash. Complex PLDs (CPLDs) are formed from a number of SPLDs connected together by a programmable switching matrix. CPLDs are EEPROM, flash or SRAM based.
PLDs fall under the most generic definition of application specific ICs (ASICs). (Diagram courtesy of Clive "Max" Maxfield.)