Definition: RISC-V

(Reduced Instruction Set Computer-5) An open-source architecture for designing RISC-based CPUs. Developed at the University of California, Berkeley, RISC-V is the fifth project of its type, hence the Roman numeral V. RISC-V is a 32-bit CPU with 31 general-purpose registers; however, it can also be extended to 64 bits. Because it is open source, the design can be modified by anyone.

Designed for efficient processing in embedded systems, RISC-V is an extremely streamlined architecture with eight system calls and 39 essential instructions. The base instruction set excludes multiplication and division.

RISC-V Extensions
Depending on the intended application, the RISC-V architecture can be augmented with numerous extensions such as support for 64- and 128-bit virtual memory paging, compressed instructions to save memory, multiplication and division, floating point math, bit manipulation and interrupt handling. See RISC.

RISC-V vs. ARM
RISC-V competes with ARM chips, which are the most popular RISC-based CPUs. Used in countless mobile devices, ARM designs are also found in embedded systems, desktop computers and servers. For example, the central processors in Apple's M chips are based on ARM designs (see Apple M series). While RISC-V is royalty free, ARM licensees pay fees to ARM Holdings. See ARM.