Term of the Moment
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Definition: CFET
(Complementary Field-Effect Transistor) The next-generation of field-effect transistors following GAAFET. Almost all chip circuits are built using CMOS logic, which pairs one n-type transistor (nFET) with a p-type transistor (pFET). However, a horizontal separator between the two takes up space. See GAAFET.
Stack One Over the Other
Emerging in the late 2020s, CFETs will stack the CMOS transistor pairs on top of each other, automatically doubling the density of chips. Estimates are that the first CFET chips will contain approximately 150 to 200 million transistors per square millimeter, up from the 100 million or so today.
Even More Layers
In time, the 3D architecture is expected to stack entire circuits, not just the CMOS transistors. For example, there may be layers for memory, chip control, caches, CPU cores and an AI accelerator.
A Billion Transistors on the Head of a Pin?
Stack One Over the Other
Emerging in the late 2020s, CFETs will stack the CMOS transistor pairs on top of each other, automatically doubling the density of chips. Estimates are that the first CFET chips will contain approximately 150 to 200 million transistors per square millimeter, up from the 100 million or so today.
Even More Layers
In time, the 3D architecture is expected to stack entire circuits, not just the CMOS transistors. For example, there may be layers for memory, chip control, caches, CPU cores and an AI accelerator.
Today, we can build more than 100 million transistors per square millimeter, about the same size as the head of a pin. When the 3D architecture is employed for entire circuits and not just individual transistors, the number of transistors should triple, quadruple and more. In time, a billion transistors may occupy a space no larger than the head of a pin. Stay tuned!